| CORNERSTONE RESEARCH GROUP, INC.
2750 Indian Ripple Rd. Dayton, OH 45440 | |
| Phone:
PI: Topic#: |
(937) 320-1877
Benjamin A Dietsch OSD 05-A01 Awarded: 05APR06 |
| Title: | Multiple Tamper Event Detection Sensor |
| Abstract: | Cornerstone Research Group, Inc. (CRG) proposes to design a novel multiple tamper detection and active anti-tamper (AT) scheme for use in new and existing weapon systems. A thorough understanding of tamper technologies in the industrial base is essential to developing new multi-mode detection devices. CRG will take an industrial base analysis approach to develop the data on tamper technologies in the industrial base. CRG will apply the information to design a multi-mode tamper detection tool capable of detecting and counting intrusion events and then zeroing or destroying critical weapon system components. The tamper detection tool can be embedded in a hard coat or attached directly to a subsystem board or multi-chip module (MCM). The CRG design will detect x-ray, ultrasonic, mechanical, SEM, chemical, and thermal attacks. CRG will determine the performance criteria of the detector, analyzing inputs/outputs, order of attacks, false negatives and false positives. Once a tamper event is detected, the device sends a signal to zero the MCM. CRG will leverage existing relationships with weapon system manufacturers to support the development of the technology and as an outlet for possible implementation and commercialization. |
| DYMAS RESEARCH, INC.
2910 Fox Run Dr. Plainsboro, NJ 08536 | |
| Phone:
PI: Topic#: |
(609) 275-4464
Dr. Wei Hu OSD 05-A01 Awarded: 05APR06 |
| Title: | Low Profile Multi-Mode Tamper Detection Sensors |
| Abstract: | DOD increasingly relies on advanced technology in its weapons for effectiveness on the battlefield. Military technology can be compromised following foreign sales to an ally, accidental loss, or capture during a conflict by an enemy. Anti-tamper (AT) is defined as the systems engineering activities intended to prevent or delay exploitation of essential or critical technologies in U.S. weapon systems. Detection of tamper events is key to anti-tamper technology. In this SBIR program, scientists at Dymas Research propose to develop a novel, miniature, low-cost tamper sensor, which is able to detect various tamper events. The experience gained in the previous development will greatly leverage and benefit to the proposed program. |
| IRVINE SENSORS CORP.
3001 Redhill Avenue, Building #3-108 Costa Mesa, CA 92626 | |
| Phone:
PI: Topic#: |
(714) 444-8715
Dr. Volkan Ozguz OSD 05-A01 Awarded: 05APR06 |
| Title: | Low Profile Ultra Thin Anti Tamper Sensor |
| Abstract: | Protection of Critical Technologies (CT) requires Anti-Tamper (AT) techniques to protect, detect and react to reverse engineering attacks. The objective of this program is to develop a multi-mode, low profile tamper detection sensor capable of detecting a wide range of tamper events while remaining difficult to identify or disable by a reverse engineer. ISC's miniaturization packaging is a technology enabler for "low profile" integrated sensors. This effort will study manufacturing materials and processes to embed COTS components using Irvine Sensors unique technology tool set for this application. The program will focus on the manufacturability to integrate certain types of sensors and meets the manufacturing related SBIR priority status under Executive Order 13329. The ISC team will investigate various techniques of reverse engineering, determine the optimum sensor requirements, design a low profile sensor concept and report on measures of effectiveness based on a wide range of commonly expected tamper events. A plan to verify AT implementation through the ISC's process flow and additional system level procedures will be analyzed. This study will lead to an "advanced development" of hardware for hardware-in-the-loop testing in a potential phase II program. |
| RADIANCE TECHNOLOGIES, INC.
350 Wynn Drive Huntsville, AL 35805 | |
| Phone:
PI: Topic#: |
(937) 320-0951
Mr. Joseph Frederick OSD 05-A01 Awarded: 05APR06 |
| Title: | Low Profile Multi-Mode Tamper Detection Sensors |
| Abstract: | The objective of this proposed effort is to research, develop and demonstrate a prototype of a multi-mode low profile sensor that will detect a wide range of reverse engineering attacks. This will be accomplished by creating a multi-layered sensor architecture into which a myriad of AT Sensors can be inserted. This effort uses the multi-layered approach to employ two complementary AT sensor technologies: micro-electro-mechanical-system (MEMS) vibrational sensors and nanoparticle doped thin film sensors. By combining these technologies, the sensor will be able to detect reverse engineering attacks from acoustic microscopy, mechanical grinding, X-rays, and focused ion beams (FIB). The effectiveness of this device will be measured in terms of metrics such as: variety of tamper events detected, shelf life, detectability, difficulty to disable once discovered, design flexibility, voltage and current characteristics under relevant environmental extremes, false alarm properties, cost, manufacturability, and operations and support (including R&M) impacts. |
| SYSTRAN FEDERAL CORP.
4027 Colonel Glenn Highway, Suite 210 Dayton, OH 45431 | |
| Phone:
PI: Topic#: |
(937) 429-9008
Mr. Robert Gillen OSD 05-A01 Awarded: 05APR06 |
| Title: | Low Profile Multi-Mode AT Sensor |
| Abstract: | Systran Federal Corp. (SFC), along with our team members, proposes to develop a low-profile, multi-mode, tamper detection sensor for the purpose of protecting sensitive hardware and data from adversaries and reverse engineers. Several separate anti-tamper (AT) techniques currently exist, but are inadequate because of high cost, lack of effectiveness, difficulty in use, unreliability, and inability to work together in a single, multi-mode sensor. SFC will address these problems by both refining existing techniques and developing new techniques and schemes for putting these into practice. For example, our previously developed active AT circuit board coatings will be redesigned with materials that can detect several types of intrusion. We will rely on our previous AT experience for near-term solutions, while exploring advanced long-term AT techniques using technologies such as MEMS and nanotechnology. |
| SPACE PHOTONICS, INC.
700 Research Center Blvd. Fayetteville, AR 72701 | |
| Phone:
PI: Topic#: |
(479) 251-7884
Mr. Matthew Leftwich OSD 05-A02 Awarded: 14JUL06 |
| Title: | Novel, Non-Intrusive Nanodeposition Technique for the Deposition of a Variety of Hardware Anti-Tamper Coatings |
| Abstract: | This effort will focus on identifying new hardware design and protection techniques and technologies that will delay reverse engineering and exploitation, slowing an adversary as much as possible in compromising U.S. technologies when they fall under their control. To date, much Government and industry effort has focused on passive board/chip coatings and self-destruct concepts, but as the DoD AT organizations have evaluated them, the effectiveness and PEO and PM acceptance of these types of techniques has been limited. Other concepts that have been assessed by the AT community include manufacturing processes, obfuscation, encryption, active coatings, volume protection and other such techniques, and a variety of these and others will be evaluated during this proposed Phase I effort and during subsequent Phase II and other follow-on efforts. This effort will therefore focus on developing innovative deposition techniques utilizing a variety of emerging nanoparticle-based nano-coatings (NanoMesh) as one of several key non-intrusive hardware anti-tamper techniques (NIHATT) that may be applied to a variety of classified military, defense, and security devices. |
| SYSTRAN FEDERAL CORP.
4027 Colonel Glenn Highway, Suite 210 Dayton, OH 45431 | |
| Phone:
PI: Topic#: |
(937) 429-9008
Mr. Robert Gillen OSD 05-A02 Awarded: 18JUL06 |
| Title: | Intrusion Sensitive Material |
| Abstract: | Systran Federal Corp. (SFC), along with our team members, proposes to develop an active circuit board coating which acts as a detection sensor for the purpose of protecting sensitive hardware and data from adversaries and reverse engineers. Several anti-tamper (AT) coating techniques currently exist, but are inadequate because of high cost, lack of effectiveness, difficulty in use, and unreliability. SFC will address these problems by both refining our existing techniques and developing new techniques and schemes for putting these into practice. We will rely on our previous AT experience for near-term solutions, while exploring advanced long-term AT techniques using technologies such as Direct Write technology. Especially important will be the performance of the coatings in extreme environments. |
| ENGINEERED COATINGS, INC.
P.O. Box 4702 Parker, CO 80134 | |
| Phone:
PI: Topic#: |
(303) 593-0588
Dr. Frank M. Kustas OSD 05-A03 Awarded: 05APR06 |
| Title: | Analyses of Coating Materials/Deposition Techniques and Device Designs for FIB-Resistant Systems |
| Abstract: | The Office of the Security of Defense requires the development of novel methods or materials for circuitry or critical systems that are resistant to FIB examination. Application of new materials or device designs that retard the effectiveness of FIB probing must also offer minimal degradation in the normal performance of the devices. Engineered Coatings, Inc. and Analytical Solutions, Inc. propose to conduct a requirements analysis and then analytical studies to trade and rank candidate coating materials and device design modifications that will degrade the performance of FIB operation and/or induce vacuum system contamination. Key properties of candidate coating materials and device designs will be collected with subsequent analysis to trade against the requirements and enable a down-selection to the most promising coating and/or device design. Coating deposition methods, whether global or local, will also be evaluated for compatibility with normal device manufacturing operations. A design document will be developed that includes the requirements analysis, solution down-selection, and preliminary fabrication processing specifications. Plans for Phase II will be developed including fabrication of a brass board prototype article for subsequent FIB examination and demonstration of the effectiveness of the FIB-resistant technology. |
| RADIANCE TECHNOLOGIES, INC.
350 Wynn Drive Huntsville, AL 35805 | |
| Phone:
PI: Topic#: |
(937) 320-0951
Mr. Joeseph Frederick OSD 05-A03 Awarded: 07APR06 |
| Title: | Focused Ion Beam (FIB) Resistant Systems |
| Abstract: | The objective of this research is to develop and demonstrate a nanoparticle-loaded thin film that can detect and discriminate X-ray and focused ion beam (FIB) radiation for tamper protection. The film can be micro-patterned directly onto electronic packages as an anti-tamper (AT) device. Research will include illuminating the film with X-ray or FIB radiation that will produce flashes of light which can be detected with on-chip optoelectronics. The film material can be patterned onto nanoporous ceramic that is used in the electronic component packaging process. Successful research and development could allow this film to be applied to the surface of the component ceramic cap and to the underside of the chip to provide low profile protection against X-ray and FIB attacks. It can also be embedded in the chip ceramic cap material where it would remain latent until it senses interrogation by X-ray or FIB radiation. The film requires no maintenance and since the material is highly stable it carries an extensive shelf life. |
| XIMAX TECHNOLOGIES CORP.LTD.
13555 Breton Ridge, #326 Houston, TX 77070 | |
| Phone:
PI: Topic#: |
(240) 461-8323
Dr. Xiqun Zhu OSD 05-A03 Awarded: 15MAY06 |
| Title: | Focused Ion Beam (FIB) Resistant Systems |
| Abstract: | We propose a circuit design approach to enhance the tamper resistance against Focused Ion Beam (FIB) probing. Our approach is to break SINGLE clock network into MULTIPLE clock domains with the identical frequencies and phases. In the proposed clock generators design, the clock frequency for all domains will be kept within a small variation range. Therefore, FIB probing operation needs to keep up with the chip normal operation speed. However, the most advanced probe will increase the loading on the targeting nodes by at least one order of magnitude; the probed nodes will switch much slower than their normal operation speed. Thus a slower clock signal is required in order to get valid data stream from the probing nodes. Since the proposed clocking strategy will not allow clock slow down, the chip under probing can not function properly. The first order estimation shows that the difficulty to overcome this clock strategy increases exponentially with the number of the clock domain increasing. In contrast, the area/power penalty increases linearly with the number of clock domain increasing. |
| EIC LABORATORIES, INC.
111 Downey Street Norwood, MA 02062 | |
| Phone:
PI: Topic#: |
(781) 769-9450
Dr. Dharmasena Peramunage OSD 05-A04 Awarded: 05JUL06 |
| Title: | Long-lived Power Source with Pulsed Current Capability |
| Abstract: | The development of a battery-based power source for active anti-tamper technology is proposed. The battery will provide both primary power for tamper-detection sensors and secondary, latent power for tamper response. A hierarchical approach is proposed in which the battery is the core element providing power to the anti-tamper sensor and response components. A second level of anti-tamper protection is provided by an innovation in the battery design that initiates an anti-tamper response if an attempt is made to penetrate or disable the battery. A third level of anti-tamper protection is provided by using the battery as a protective cover for critical components. The key innovations are the selection of battery materials that provide a 10-year functional lifetime with pulsed-current capability, and the a packaging design that prevents undetected tampering of the battery. A dual-chemistry battery cathode is proposed that combines two active materials that together provide long-lived, low-level primary power and an on-demand pulsed secondary current capability. The principal Phase I objective is to fabricate a battery incorporating elements that detect battery tampering and to demonstrate the primary and secondary power capabilities of the battery. |
| QYNERGY CORP.
3800 Osuna Road NE, Suite 2 Albuquerque, NM 87109 | |
| Phone:
PI: Topic#: |
(505) 890-6887
Dr. Christopher Eiting OSD 05-A04 Awarded: 05JUL06 |
| Title: | Innovative Anti-Tamper Power Source |
| Abstract: | Qynergy Corporation proposes to develop a unique power system for anti-tamper applications. Anti-tamper technology is used for protecting critical technology from being reverse engineered. Qynergy has developed a unique technology that converts energy from beta emitting radioisotopes into usable power. This QynCellT (betavoltaic power cell) is capable of delivering small amounts of power (micro to milliwatts) for long periods of time. The QynCellT is a solid state device and is hence capable of operating under the extreme temperature conditions necessary for anti-tamper applications. Successful completion of the proposed effort will result in the confirmation of the technical feasibility of the QynPackT for anti-tamper applications. It would answer all of the questions related to integration of the QynCellT to storage systems and position the technology for prototyping. At the end of Phase I, Qynergy will have identified an anti-tamper technology, designed a QynPackT and proven its feasibility for the prototype power cell that would be fabricated, integrated and tested with an anti-tamper device in Phase II. Primary uses of the QynCellT will be in applications where conventional batteries, solar cells and/or Plutonium-fueled radioisotope thermal generators (RTGs) are not practical. In most cases, the power solution will be constrained by the need to minimize the signature of the application, inability to recharge batteries due to remote operating conditions, or a need to avoid the use of highly energetic radioisotopes such as 33Pu. Such areas include power for remote sensors and space. |
| BARRON ASSOC., INC.
1410 Sachem Place, Suite 202 Charlottesville, VA 22901 | |
| Phone:
PI: Topic#: |
(434) 973-1215
Mr. Alec J. Bateman OSD 05-A05 Awarded: 07APR06 |
| Title: | Development of an Anti-Tamper Operational Environment Sensor |
| Abstract: | "Black-box" attacks have the potential to significantly diminish the technological advantage of the U.S. military while requiring relatively modest resources on the part of an adversary. The "black-box" attack is an attempt to understand the functionality of a system from an input-output perspective, without the need to fully reverse engineer the implementation. The attack typically involves testing a system in a laboratory environment where a wide range of input conditions can be systematically introduced. The knowledge gained from such an attack can be used effectively to develop countermeasures to U.S. systems. Anti-tamper hardware technology is needed to thwart such attacks and protect critical program information. We propose a research effort to develop an operational environment sensor to address the anti-tamper hardware need. During a "black-box" attack in a laboratory environment, the system configuration will typically be altered in some fashion to facilitate testing. Such alteration will affect the characteristics of the RF spectrum emitted by the device. Our approach employs an RF sensor capable of sweeping through a broad frequency range and detecting changes in the characteristic spectrum, which will be indicative of an attack. |
| DBI
101 Lacey's Spring Drive Lacey's Spring, AL 35754 | |
| Phone:
PI: Topic#: |
(256) 881-9372
Dr. David M. Burns OSD 05-A05 Awarded: 11APR06 |
| Title: | Anti-Tamper Operational Environment Sensors |
| Abstract: | The objective of this investigation is to demonstrate an innovative sensor designed to detect when a system has been removed from its operational environment. |
| EDAPTIVE COMPUTING, INC.
1245 Lyons Road, Building G Dayton, OH 45458 | |
| Phone:
PI: Topic#: |
(937) 281-0792
Dr. John Bellando OSD 05-A05 Awarded: 07APR06 |
| Title: | Anti-Tamper Operational Environment Sensors |
| Abstract: | Our proposal specifically addresses the stated requirements of the solicitation; we will develop and deploy tools, methods, and models for a low profile sensor capable of distinguishing a system's operational environment from a test environment in order to defend against "black box" attacks. . The proposed EDAptiver SAMURAIT solution builds on previous EDAptive Computing, Inc (ECI) knowledge and technology - itself innovative - to include a robust, non-interference, adaptable solution to providing anti-tamper monitoring of the environment under which a critical asset is functioning. The resulting capabilities will result in a "design for anti-tamper" methodology and tools with which we will monitor and protect a critical system component from extensive testing within a simulated environment, known as black box testing. The SAMURAI solution, complete with anti-tamper protection in the form of system monitoring and obfuscation, will then be synthesized and deployed within U.S. weapon systems. ECI will employ adaptive learning techniques to ensure robustness of the solution for a variety of military components and systems. Prior experience and new research has already shown that ECI's innovative tools suite will be clearly adaptive to OSD needs and operational conditions. |
| NVE CORP. (FORMERLY NONVOLATILE ELECTRONICS, INC.
11409 Valley View Road Eden Prairie, MN 55344 | |
| Phone:
PI: Topic#: |
(952) 918-1155
Dr. Peter Eames OSD 05-A05 Awarded: 01MAY06 |
| Title: | Magnetic Operational Environment Sensor |
| Abstract: | This Phase I SBIR program will design and manufacture an environmental sensor that is sensitive to the earth's magnetic fields. The device is ideal for "black-box" attacks because it is sensitive to changing environmental conditions with and without power. The sensor requires no internal power supplies or batteries. The device is microelectronic compatible which allows it to be very small and extremely versatile. The "black box" can be many sizes and shapes from miniaturized microelectronic systems to large shipping containers. The device can be custom packaged or fully integrated with other ICs at the wafer level. The device works by storing one vector component of the earth's ambient magnetic field in a magnetically unstable array of lithographically patterned magnetic elements. When the protected volume is rotated, turned, or tilted, the sensor is exposed to varying ambient magnetic fields. This upsets the alignment of the magnetic elements, which can then be read when power has been restored. The sensor could be used to signal a self-destruct of critical systems or signal the erasure of important data. |
| SYSTRAN FEDERAL CORP.
4027 Colonel Glenn Highway, Suite 210 Dayton, OH 45431 | |
| Phone:
PI: Topic#: |
(937) 429-9008
Mr. Robert Gillen OSD 05-A05 Awarded: 07APR06 |
| Title: | AT Operational Environment Sensor |
| Abstract: | Systran Federal Corp. (SFC), along with our distinguished research partner, proposes to develop an operational environment sensor for the purpose of protecting sensitive hardware and data from adversaries and reverse engineers by alerting a system when it has been removed from its intended environment and brought to a laboratory for reverse engineering. We will make use of a very novel, low-profile, zero-power varactor shunt switch developed by Dr. Guru Subramanyam of UDRI. This switch will act as a versatile proximity sensor that can be featured in a number of different sensor architectures. From an Anti-Tamper (AT) design perspective, this solution is excellent in that it is simple, compact and low-profile, is difficult to detect and to reverse engineer once detected, offers flexibility to be incorporated into many anti-tamper designs, should be stable under a wide range of environmental conditions, and is low-cost and low-power. These attributes make these proximity sensors difficult to detect, simple to monitor, and easy to integrate into a new or legacy system. This technology should also be easy to maintain over the life of the operational system and have a long shelf life. |
| AERONIX, INC.
1775 W. Hibiscus Blvd., Suite 200 Melbourne, FL 32901 | |
| Phone:
PI: Topic#: |
(321) 984-1671
Mr. Jeff Fisher OSD 05-A06 Awarded: 26MAY06 |
| Title: | Secure Trusted Computing System-on-Chip |
| Abstract: | Many currently fielded DoD electronic systems contain sensitive and sometimes classified software applications. These sophisticated systems incorporate embedded COTS processing devices which make them susceptible to reverse engineering using commercial off the shelf tools including emulators and debuggers. To address this problem, various anti-tamper techniques have been employed. Traditionally, these have been either at the device level or at the card/box boundary level. Each of these approaches has its benefits and drawbacks. Chip level coatings can be costly to apply, due to the special procedures and process steps outside of the normal semi-conductor fabrication flow. They also tend to have higher yield losses caused by the protective technology itself. These coatings are limited to protecting the sensitive information contained within a single device (or within a protected cavity such as a multi chip module). On the other hand, card and box level tamper mechanisms protect the information flow within a larger area of interest. Their limitation is that if an adversary is able to circumvent the tamper mechanism, all internal information is then available. The specific problem addressed by this SBIR is the protection of sensitive or classified information flowing between devices within a card and or a collection of circuit cards (e.g. box, sub-system, system). A family of system on a chip (SOC) components will be developed to support this paradigm. These devices will incorporate many of the Crypto Modernization tenets identified and developed by the NSA. The devices will be fabricated using the DoD/NSA sponsored trusted foundry facilities. They will be referred to throughout this proposal as the Trusted System on a Chip (TSOC). |
| CORRENT CORP.
1711 West Greentree Drive, Stuite 201 Tempe, AZ 85284 | |
| Phone:
PI: Topic#: |
(480) 648-2360
Mr. Richard Takahashi OSD 05-A06 Awarded: 21MAY06 |
| Title: | Secure Trusted Computing System-on-Chip |
| Abstract: | This SBIR Phase 1 project proposes the feasibility study of secure trusted computing System-on-Chip. To prevent or delay the compromise of Critical Program Information, DoD is seeking operational embedded technology to provide the real-time encryption and authentication and "other" capabilities for protecting and processing information in tactical systems. Also, technology shall detect tampering of the element and Zeroize mission critical information to deter reverse engineering efforts. One avenue worth exploring to this end is the development of the secure trusted system-on-chip (SOC). Using a superset of Trusted Computing Group TPM standard logic embedded with a 32 bit RISC processor and collateral interfaces, a trusted SOC would provide a feasible solution to this need-which would also include a streaming encryption capability, and universal I/O for easy utilization. The trusted SOC would be embedded to secure a given system with anti-tamper capabilities. Our anti-tamper circuits will be all digital making the design portable across different foundries and processes. Our multi-layered approach to security protects against single point of failure thus making it extremely difficult to extract information, especially if the attacker has access to only a few chips. A concept design specification will be delivered at the conclusion of the project. |
| CORNERSTONE RESEARCH GROUP, INC.
2750 Indian Ripple Rd. Dayton, OH 45440 | |
| Phone:
PI: Topic#: |
(937) 320-1877
Dr. Richard D Hreha OSD 05-A07 Awarded: 05MAY06 |
| Title: | Assured Sanitization of Stored Data |
| Abstract: | Cornerstone Research Group, Inc., proposes to evaluate and analytically validate the technical feasibility of three concepts for new materials and processes enabling data storage that can be discreetly sanitized by a mobile system operator under duress. In a manner analogous to burning paper documents and pulverizing their ashes, the technology resulting from this program will use materials and processes whose physics of erasure preempt any possible reconstruction of the original data. These new technology concepts include substitute materials for CD/DVD and hard drives and an entirely new optical data storage technology based on novel liquid crystal materials. Each concept offers a new data sanitization mechanism that poses no danger to the operator, can be easily and discreetly actuated, and will render the data forensically irrecoverable. Phase II development of technology found feasible in Phase I will yield significant advancement in the data protection vital for maintaining the current U.S. leadership in warfare technology. |
| LEWIS INNOVATIVE TECHNOLOGIES, INC.
P. O. 624, 534 Lawrence Street Moulton, AL 35650 | |
| Phone:
PI: Topic#: |
(256) 905-0775
Mr. James M. Lewis OSD 05-A07 Awarded: 12MAY06 |
| Title: | Techniques and Processes for Rendering Mobile Technology Forensically Irrecoverable |
| Abstract: | LIT Recommends: 1. Developing Self-Modifying FPGAs that self-scramble or destroy their own configuration EEPROM. 2. Evaluating Encrypted Memory Controller that encrypts data files. Data can be read back only through controller which may be destroyed if compromised. 3. Retrieval/destruction Initiation techniques which include: (a) Mechanical Actuation (b) External Key Actuation - using a real time clock module and/or miniature GPS module (or other RF key) so that data can only be retrieved at a specific time and location or only in the presence of a predefined serial or RF key. Attempted unauthorized access would then result in initiation of data destruction process. (d) Extended Timing - self destruct auto-initiates if the device is not recovered or accessed within a predetermined time. This technique is similar to item b except that no unauthorized access is required to start self destruct. This technique would be useful in applications such as missiles that should reach maximum range in a predetermined time or data loggers that should be recovered before a specific interval has expired. |
| SPACE PHOTONICS, INC.
700 Research Center Blvd. Fayetteville, AR 72701 | |
| Phone:
PI: Topic#: |
(479) 251-7884
Mr. Matthew Leftwich OSD 05-A07 Awarded: 12MAY06 |
| Title: | Investigation of a Novel, Nano-Hardware Lock and Associated Software Anti-Tamper Techniques for Secure Memory and Memory Eraser Applications |
| Abstract: | The NESL concept uses three techniques to form a protective shield around modern computer systems. The first layer is a novel method for generating and locking cryptographic keys to a unique computer system. The proposed, novel key locking system, though relatively simple, takes advantage of the complex and disparate natural phenomena occuring in a common nanomaterial. The second and third layer leverage this novel key system to protect primary and secondary memory from exploitation through encryption. The secondary memory system is protected with an encrypted file system, and the primary memory is protected with encryption when outside of the CPU. |
| INFOSCITEX CORP.
303 Bear Hill Road Waltham, MA 02451 | |
| Phone:
PI: Topic#: |
(781) 890-1338
Dr. Robert F. Kovar OSD 05-A09 Awarded: 22JUN06 |
| Title: | Multi-Functional, Light-Cured, Anti-Tamper Coating |
| Abstract: | The DoD has identified the need for advanced Anti-Tamper (AT) technologies to protect critical U.S. technologies from exploitation via reverse engineering. Current anti-tamper coating techniques commonly involve the use of flame-sprayed ceramic coatings for electronic components, which can cause thermal damage to underlying circuitry during application at elevated temperature. Infoscitex (IST) proposes to develop a sprayable, light-curable, anti-tamper coating (LCATC) that cures rapidly at ambient temperature into an adherent, multifunctional tamper-resistant coating. This low temperature cure capability coating system protects sensitive electronic components from potential thermal damage. The cured LCATC is hard, adherent, opaque to visible and infrared light, and obscures visualization by X-rays. It adheres strongly to electronic components and substrate, and is so durable that attempts to remove the coating by mechanical or chemical means destroys all evidence of underlying circuits and interconnects. In Phase I, IST will develop the LCATC, spray-coat simulated electronic component test specimens and demonstrate the ability to light-cure the LCATC into durable coatings that resist tampering via optical, mechanical and chemical methods. In Phase II, IST will refine and scale-up the LCATC, produce coated electronic components and initiate commercialization. |
| SPACE MICRO, INC.
12872 Glen Circle Road Poway, CA 92064 | |
| Phone:
PI: Topic#: |
(858) 332-0702
Dr. Michael Featherby OSD 05-A09 Awarded: 31MAY06 |
| Title: | Non-Thermally Cured, Active Coatings for Anti-Tamper Protection |
| Abstract: | The use and effectiveness of anti-tamper technologies will help to more readily bring means of protecting our technology to a point of maturation that allows them to be used in current and new systems. To assist in this process, the efforts proposed here will provide Army and other DoD Program Managers a more cost effective set of tools to implement anti-tamper processes in critical U.S. electronics systems. The focus here is on innovative techniques to foil an adversary's reverse engineering of electronics microelectronics, modules, and boards. The approach described herein highly leverages cutting-edge existing commercially available semiconductor processes such as combustion chemical vapor deposition (CCVD) and atomic layer deposition (ALD), uniquely combined with fillers such as emerging nanotechnology materials (e.g. carbon nanotubes and buckyballs). The combination of these technologies appears to hold great promise for providing an effective anti-tamper approach. |
| SPACE PHOTONICS, INC.
700 Research Center Blvd. Fayetteville, AR 72701 | |
| Phone:
PI: Topic#: |
(479) 251-7884
Mr. Matthew Leftwich OSD 05-A09 Awarded: 14JUN06 |
| Title: | Novel, Non-Intrusive Nanodeposition Technique for the Deposition of a Variety of Hardware Anti-Tamper Coatings |
| Abstract: | This effort will focus on identifying new hardware design and protection techniques and technologies that will delay reverse engineering and exploitation, slowing an adversary as much as possible in compromising U.S. technologies when they fall under their control. To date, much Government and industry effort has focused on passive board/chip coatings and self-destruct concepts, but as the DoD AT organizations have evaluated them, the effectiveness and PEO and PM acceptance of these types of techniques has been limited. Other concepts that have been assessed by the AT community include manufacturing processes, obfuscation, encryption, active coatings, volume protection and other such techniques, and a variety of these and others will be evaluated during this proposed Phase I effort and during subsequent Phase II and other follow-on efforts. This effort will therefore focus on developing innovative deposition techniques utilizing a variety of emerging nanoparticle-based nano-coatings (NanoMesh) as one of several key non-intrusive hardware anti-tamper techniques (NIHATT) that may be applied to a variety of classified military, defense, and security devices. |
| SYSTRAN FEDERAL CORP.
4027 Colonel Glenn Highway, Suite 210 Dayton, OH 45431 | |
| Phone:
PI: Topic#: |
(937) 429-9008
Mr. Robert Gillen OSD 05-A09 Awarded: 19JUN06 |
| Title: | NTC Active AT Coatings |
| Abstract: | Systran Federal Corp. (SFC), along with our team members, proposes to develop a low-temperature, active circuit board coating which acts as a detection sensor for the purpose of protecting sensitive hardware and data from adversaries and reverse engineers. Several anti-tamper (AT) coating techniques currently exist, but are inadequate because of high cost, lack of effectiveness, difficulty in use, and unreliability. SFC will address these problems by both refining our existing techniques and developing new techniques and schemes for putting these into practice. We will rely on our previous AT experience for near-term solutions, while exploring advanced long-term AT techniques using technologies such as MEMS and nanotechnology. |
| TRITON SYSTEMS, INC.
200 TURNPIKE ROAD Chelmsford, MA 01824 | |
| Phone:
PI: Topic#: |
(978) 250-4200
Dr. Scott Morrison OSD 05-A09 Awarded: 30MAY06 |
| Title: | Novel Anti-Tamper Coatings for Microelectronics(1000-812) |
| Abstract: | Triton Systems, Inc. responds to Army's need to This proposal addresses the Army's need to develop innovative tamper-proof, non-thermally cured coatings which prevents unauthorized individuals from reverse engineering of military microelectronics. We propose to develop tamper-proof, and photo-curable coatings that will protect military electronics against electromagnetic field (EMF), optical, X-ray and acoustic tools for reverse engineering. During the Phase I, Triton will demonstrate the feasibility studies to develop a photo-curable coating that will provide anti-tampering protection for circuit boards and military microelectronics. During Phase II, we will develop a design of experiments for the selected non-thermal curing coatings that were identified in Phase I for reliability and environmental testing of a fabricated prototype at Army testing facility. The performance of this fabricated prototype against multiple reverse engineering methods will demonstrate the effectiveness of the protection material's capability, based on successful Phase I results, and will demonstrate its effectiveness in several field tests. |
| ACCORD SOLUTIONS, INC.
3533 Albatross Street San Diego, CA 92103 | |
| Phone:
PI: Topic#: |
(619) 692-9476
Dr. Carl G. Murphy OSD 05-A10 Awarded: 26JUN06 |
| Title: | Secure Processors |
| Abstract: | Accord proposes a pioneering and innovative code-to-machine execution technology that preserves the encryption of executable instructions and data throughout all aspects of the execution cycle. At no time are instruction words or data values unencrypted. Crypto-reduced-instruction-processor-trusted-compu ters (CRIPTC) are not dependent upon reconfiguration or on machine uniqueness. CRIPTC memory and support chips are conventional. A CRIPTC machine has no standard functional units; each unit is synthesized by a crypto-synthesis compiler code builder combining aspects of cryptographic, very-long-instruction-word RISC compilers, hardware netlist synthesizers and chip place & route. The resulting CRIPTC instruction words form encrypted higher-level functional units. A 32-bit word has a key search space significantly greater than a 256-bit AES encryption. CRIPTC is a secure computer ideally suited to protecting critical technology in embedded real time or complex command and control processing. CRIPTC-based secure processing can be distributed outside secure sites, and applied within units which are subject to enemy capture. Accord will demonstrate a SystemC reference design that simulates bit-and-clock-accurate execution of the "never decrypted" CRIPTC instruction stream. |
| ARXAN RESEARCH, INC.
3000 Kent Avenue, Purdue Technology Center West Lafayette, IN 47906 | |
| Phone:
PI: Topic#: |
(765) 775-1004
Mr. Eric D. Bryant OSD 05-A10 Awarded: 21JUL06 |
| Title: | Security Amplification Through Data Splitting: Achieving High Security Using Moderately Secure Hardware |
| Abstract: | For this project, we will research novel data-splitting techniques that can be used on COTS hardware to achieve similar effects as a specialized security processor, without relying upon expensive cryptographic operations. This is achieved through the technique of data splitting, and the use of k copies of the same moderately secure COTS hardware (where k is at least 2, and can be increased to increase the resulting security). If the probability of compromise of the data in the COTS hardware is p, then the probability of compromise of the proposed system is p^k because it is now necessary to completely compromise every one of the k copies to obtain the secret encryption keys or otherwise compromise the secret data. |
| CGO
3260 Clovewood Ln San Jose, CA 95132 | |
| Phone:
PI: Topic#: |
(408) 507-8359
Dr. Sukarno Mertoguno OSD 05-A10 Awarded: 26JUN06 |
| Title: | Secure Processors |
| Abstract: | This proposal described a family of techniques for providing code encryption beyond the first level of security provided by encrypting code and data in the memory and decrypting code and data in the caches inside the processor. The proposed technology, Deep Code Scrambling (DCS), was designed to work beyond and in conjunction with the first level of security, and hence providing a second level of security. In DCS, the decrypted code in the caches are virtual or scrambled codes, which need to be unscrambled in one of the processor pipeline stage before they become meaning full for the rest of the processor pipeline stages. Further more the Unscrambling key changes often and randomly, and hence providing another barrier for reverse engineering the internal algorithms of the codes. |
| SPACE MICRO, INC.
12872 Glen Circle Road Poway, CA 92064 | |
| Phone:
PI: Topic#: |
(858) 332-0701
Mr. David R. Czajkowski OSD 05-A10 Awarded: 08JUN06 |
| Title: | Secure Processor using Opcode Diversity |
| Abstract: | Space Micro's Processor with Opcode Diversity (POD) is built from Space Micro's innovative security elements and tools, including our patent pending Object Level FirewallsT and AutoSafeT security technologies. The combination provides a low risk path for the development of a microprocessor integrated circuit that protects software and operating systems from software engineer's development station, through delivery and while operating in the POD. All elements of the POD are fully protected, including cache, execution units, input/output buses and external memory. Design features prevent access to executing opcodes while in operation. Space Micro's security technologies provide the capability to tie specific software to specific POD processors and authorized personnel, plus the capability to set security policy within the software itself. AutoSafe also addresses the software development environment and management of encryption keys, creating a system that can be used by minimally trained field personnel, plus automatically develop secure software with Protect, Detect and React capabilities. |
| CORRENT CORP.
1711 West Greentree Drive, Stuite 201 Tempe, AZ 85284 | |
| Phone:
PI: Topic#: |
(480) 648-2360
Mr. Richard Takahashi OSD 05-A11 Awarded: 13JUN06 |
| Title: | Secure Memory for Anti-Tamper (AT) Application |
| Abstract: | This SBIR Phase 1 project proposes the feasibility study of an integrated secure memory architecture for storage of critical software code such as encryption keys; capable of securely, quickly and reliably erasing that code in a minimal or no-power state in the event of tamper or directed destruction. In a tactical or time critical situation, conventional memory wipe processes are too lengthy to complete. A better alternative to overwriting clear memory to an acceptable randomness is needed. It must leave memory effectively in a random state, and execute completely in milliseconds. A valid approach for these objectives is to use a system of encrypted memory. The data stored in memory, would appear to be effectively random without access to the keys and decryption mechanism. If data is encrypted with a strong algorithm which induces variability in the encrypted data, it is a practical impossibility to brute force decode the data without access to the key. Improperly secured key information compromises the encrypted data stored, a level of tamper security is required to prevent operation outside a specified range of operation thwarting some probing or reverse engineering attacks. A concept design specification will be delivered at the conclusion of the project. |
| LEWIS INNOVATIVE TECHNOLOGIES, INC.
P. O. 624, 534 Lawrence Street Moulton, AL 35650 | |
| Phone:
PI: Topic#: |
(256) 905-0775
Mr. James M. Lewis OSD 05-A11 Awarded: 05JUN06 |
| Title: | Secure Memory for Anti-Tamper (AT) Application |
| Abstract: | LIT proposes developing non-volatile memory constructed from blocks of SRAM configured for fast block erasure using a parallel erase technique. LIT proposes a memory controller capable of quickly rendering the data useless by means of a proprietary technique. |
| NVE CORP. (FORMERLY NONVOLATILE ELECTRONICS, INC.
11409 Valley View Road Eden Prairie, MN 55344 | |
| Phone:
PI: Topic#: |
(952) 996-1636
Dr. James Deak OSD 05-A11 Awarded: 07JUN06 |
| Title: | Zero-Remanence Anti-Tamper Cryptokey Storage Device |
| Abstract: | The goal of this Small Business Innovation Research Phase I project is to research and develop a low-power, fast, non-volatile memory sufficient in size for storing encryption keys that has the capability to "zeroize" itself without data remanence in response to tampering and without applied power using a permanent magnet based technique. The device is intended for volumetric protection of analog and digital electronics systems. In addition to self-zeroization, the device has the capability to signal that a tampering event has occurred. The proposed anti-tamper memory device can be reprogrammed indefinitely and read by the protected hardware using a standard interface. Initially the device will be implemented as a stand-alone cryptokey memory for volumetric anti-tamper applications, but with further research and development, memory capacity could be increased, and it could be embedded into an integrated circuit package for protection of custom application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or microcontrollers. The phase I program will use a combination of experiment and modeling to evaluate the effectiveness of the zeroization mechanisms, power requirements for reading and writing the device, and manufacturing feasibility. |
| PHYSICAL OPTICS CORP.
Photonic Systems Div, 20600 Gramercy Pl, Bldg 100 Torrance, CA 90501 | |
| Phone:
PI: Topic#: |
(310) 320-3088
Dr. Fang Zhang OSD 05-A11 Awarded: 08JUN06 |
| Title: | Anti-Tamper Optical Secure Read/Write/Erase Memory |
| Abstract: | To address the need for secure memory that can store and protect sensitive information and securely zeroize itself if tampering occurs, Physical Optics Corporation (POC) proposes to develop a new Optical Secure Read/Write/Erase Memory (OSRWEM) system based on crosslinkable liquid crystal, a tunable liquid crystal source, a CCD chip, and use of light shaping diffuser with a tunable light source, which is a mature POC technology. This marks the ODRWEM structure compact, economical, similar to a flash memory in a cell phone. This read/write/erase nonvolatile memory can securely erase stored information, and is itself secure from unauthorized reading and X-ray tampering. In addition, the memory can be permanently destroyed by application of a few volts, making reverse engineering impossible. In Phase I POC will show the feasibility of the OSRWEM system by demonstrating its features in a simplified assembled system. In Phase II POC plans to develop a prototype to show how the OSRWEM can act as nonvolatile memory that can securely clear all sensitive information, and thus protect against successful tampering. |
| STRUCTURED MATERIALS INDUSTRIES
201 Circle Drive North, Unit # 102 Piscataway, NJ 08854 | |
| Phone:
PI: Topic#: |
(732) 302-9274
Dr. Edwin M. Dons OSD 05-A11 Awarded: 20JUN06 |
| Title: | Tamper Proof, Erase-on-Demand Memories |
| Abstract: | Structured Materials Industries proposes to develop a self-powered Anti-Tamper device thermalization technology that is activated by either physical tampering or in response to an electrical signal generated by controller self-destruct circuitry or tampering detection circuitry. We will carry out this work with a major defense contractor and will demonstrate the technology for fielded military devices. Phase I will further demonstrate the concept, Phase II will address implementation hurdles and Phase III would see defense and potentially commercial fielded devices. |
| CORNERSTONE RESEARCH GROUP, INC.
2750 Indian Ripple Rd. Dayton, OH 45440 | |
| Phone:
PI: Topic#: |
(937) 320-1877
Jason M Hermiller OSD 05-A12 Awarded: 25MAY06 |
| Title: | Anti-Tamper Diffusion Mechanisms |
| Abstract: | Cornerstone Research Group, Inc (CRG), proposes to develop an anti-tamper system that uses a diffusion mechanism to destroy a semi-conductor component upon tamper detection. CRG will integrate and apply a variety of its advanced materials technologies in a layered component-level defense. The integrated system will protect the component from tampering, safely and non-energetically destroy it if that initial defense is breached, and simultaneously protect adjacent components from collateral damage when the diffusion mechanism activates. |
| ENTERPRISE SCIENCES, INC.
14817 Silverstone Drive Silver Spring, MD 20905 | |
| Phone:
PI: Topic#: |
(301) 388-3838
Dr. Andrew Mostovych OSD 05-A12 Awarded: 22JUN06 |
| Title: | High-Voltage-Discharge Self-Destruct Mechanisms |
| Abstract: | This proposal presents a plan for developing and evaluating new high-voltage technologies capable of permanently destroying the functionality of semiconductor memory and processor circuits as well as any residual data remanence stored in these units. The envisioned technologies can be implemented on the chip, pc-board, or device platform level--equally effectively for new designs as well as retrofits of older equipment. This will allow for the quick physical self-destruction of critical components in secure systems should the systems be physically compromised. The proposed effort will evaluate, design, and demonstrate the technology in laboratory trials. The program in this proposal has the goals of laboratory implementation and verification of miniature "Marx-bank" pulsers that can be integrated into standard pc-board designs, as well as demonstration of on-command destruction of memory and processor semiconductors by high voltage discharge from these pulsers. |
| MIDE TECHNOLOGY CORP.
200 Boston Avenue Suite 1000 Medford, MA 02155 | |
| Phone:
PI: Topic#: |
(781) 306-0609
Dr. Marthinus C. van Schoor OSD 05-A12 Awarded: 31MAY06 |
| Title: | Shape Memory Alloy Destruction Mechanism (SMADM) |
| Abstract: | In the event of a physical compromise of a secure system, it may be necessary to physically disable the critical components of the system to ensure that critical hardware and software are rendered not useable for reverse engineering. Mide proposes to utilize the unique properties of shape memory alloys to fragment electrical components and boards in the event of a physical compromise. Shape memory alloys experience a transition from martensite to austenite when they are heated above their transition temperature. In martensite the material is very malleable, in austenite the material returns to its memorized shape and is capable of providing significant force. Mide proposes to memorize the shape memory alloy in a wave pattern and insert it into a PC board or electrical component. In the event of a breach, a large amount of current would surge through the electrical system destroying the software and causing the entire system to heat, which would in turn actuate the SMA to physically destroy the board. |
| NANOHMICS, INC.
6201 East Oltorf St., Suite 400 Austin, TX 78741 | |
| Phone:
PI: Topic#: |
(512) 389-9990
Dr. Don Patterson OSD 05-A12 Awarded: 24MAY06 |
| Title: | Microchip MEMS Iron Maiden |
| Abstract: | As a last resort, self-destruct technologies must be employed to protect sensitive electronic data. Squib-induced pyrotechnics and low energy electro-explosives that provide a controlled explosive force can be effective in the destruction of the silicon microchip. However, explosives and chemical reactants packaged with electronic devices pose safety, storage and disposal hazards even if the detonation mechanism is reliably safe. Likewise, electronic self-destruct methods require high power and homogenous field distribution to be effective at data disruption and run the risk of leaving the microcircuitry intact for visual inspection by an adversarial reverse engineer. As an alternative, Nanohmics proposed to develop a novel method to physically destroy the silicon microcircuity using a method of micromechanical pulverization. In this regard, a package-level MEMS device will be driven into the circuit side of a silicon microchip (e.g. microprocessor, memory, sensors). In the event of a triggered mechanical actuation , the MEMS device will impact the silicon surface resulting in massive fragmentation of the frangible silicon microchip. Physical fragmentation will render the microchip (e.g. microprocessor, flash memory, sensor) irrecoverably inoperable and the electronic content as well as the physical chip architecture untraceable. |
| QORTEK, INC.
1965 Lycoming Creek Road, Suite 205 Williamsport, PA 17701 | |
| Phone:
PI: Topic#: |
(570) 322-2700
Dr. Gareth J. Knowles OSD 05-A12 Awarded: 25MAY06 |
| Title: | Non-Energetics-Based Self-Destruct Mechanisms |
| Abstract: | The new technological approach provides ability to implement physical destruction of semiconductor devices with an inexpensive and completely silent method that is non-energetic. The approach promises to be synergistic with AT applications at the microelectronics die and wafer level and appears to be compatible with standard fabrication tools either as a standard step during manufacture or possibly as a later security add-on. It will be virtually impossible to detect. Even if an adversary were successful in bypassing security systems and gained access to the security sensitive electronics device(s), the adversary will not be aware that the device has silently undergone a complete physical destruction mode. Even if an adversary were somehow to gain prior knowledge that that the anti-tamper security had been installed, there is not a thing that the adversary can do to prevent (selectable) annihilation of the chip to the point where it would be inordinately difficult, even with layer by layer scan (ION beam), impedance or removal techniques to recover any useful on either microelectronics design or stored data. |
| GALORATH, INC.
100 North Sepulveda Blvd., Suite 1801 El Segundo, CA 90245 | |
| Phone:
PI: Topic#: |
(310) 414-3222
Mr. Daniel D. Galorath OSD 05-CM1 Awarded: 06SEP06 |
| Title: | Cost Modeling Interoperability and Integration |
| Abstract: | Cost information can improve projects and project decision making. But the project artifacts that can help determine costs are buried in enterprise systems such as supply chain, ERP, PLM, CAx and others. Although many of these systems rely on common data, differences in internal storage structures and nomenclature and lack of tool integration keeps stakeholders from receiving the decision support information needed to make programs most successful including overall costs, tradeoff capability, optimization ability, risk and uncertainty throughout the product cycle. Users must often reenter data at considerable time and expense. Some point-to-point solutions do exist between specific tools, but as the number of tools grows, this integration solution becomes unmanageable and the benefits of an integrated tool suite go unrealized. The project will integrate cost models with the artifacts using the FIPER framework resulting in better quality and reliability, improved flexibility, shorter cycle times, increased effectiveness and lower cost. This integration will result in more successful projects as managers, engineers and analysts make more informed decisions. |
| PRICE SYSTEMS, L.L.C
17000 Commerce Parkway , Suite A Mt. Laurel, NJ 08054 | |
| Phone:
PI: Topic#: |
(703) 740-0078
Mr. Larry Reagan OSD 05-CM1 Awarded: 06SEP06 |
| Title: | Cost Modeling Interoperability and Integration |
| Abstract: | Since 2000, PRICE Systems has invested over $7.9 million of our own money in the research and development of a new cost modeling framework. This framework is an open architecture which allows easier integration of cost models to other modeling environments. The intent is to develop one framework where a system can be modeled throughout its entire lifecycle. We call this methodology Affordability Simulation. The vision is to have one user interface where the system can be modeled. Through that interface, software, hardware, support, obsolescence, and any other aspect of the program can be modeled. Users would include the early designers, the program office, the implementers and logistic support teams. This requires not only a technical change, but a cultural change as well. Proven capability will help change the culture. With the funding from this OSD/DLA SBIR, PRICE Systems will expand our initial framework to include the ability to propagate the cost models through the life cycle of a program. |
| TEAMVISION CORP.
33305 1st Way South, B207 Federal Way, WA 98003 | |
| Phone:
PI: Topic#: |
(253) 661-9765
Mr. Stephen Metschan OSD 05-CM1 Awarded: 06SEP06 |
| Title: | Cost Modeling Interoperability and Integration Framework |
| Abstract: | TeamVision proposes to enhance and tailor its existing collaborative decision analysis technology, Framework CT to meet the requirements of an Integrated Threat, Mission, Performance, Design, Manufacturing, Support and Life Cycle Cost Analysis for Department of Defense (DOD) weapon systems. The result of this effort will provide the DOD with a powerful platform to design, model, and analyze systems, and coordinate related objectives from a holistic perspective. FrameworkCT is a unique and innovative approach, and its current features include an adaptive object database; enterprise-class security; Excel, MS-Project, and other desktop application integration; collaborative decision support; and massively parallel processing using networked desktop computing. This FrameworkCT `desktop application integration' approach has a significant largely untapped application potential in all areas of Enterprise Resource Planning (ERP), Manufacturing Resource Planning (MRP), and Product Data Management (PDM), and Cost as an Independent Variable (CAIV) while satisfying various additional objectives. To better align the current capabilities in Framework CT to the goals of DOD will require the integrating existing CAD/CAM/CAE and PDM systems used by DOD with FrameworkCT environment. |
| FRONTIER TECHNOLOGY, INC.
26 Castilian Drive, Suite B Goleta, CA 93117 | |
| Phone:
PI: Topic#: |
(937) 429-3302
Mr. Sam Boykin OSD 05-CM2 Awarded: 29AUG06 |
| Title: | Automated, Intelligent Life-Cycle Cost Modeling |
| Abstract: | As the longevity of weapon systems continue to increase, operations and support (O&S) costs account for a larger percentage of the total system life-cycle cost. Yet O&S costs are often under estimated, especially early in the development cycle when 80% or more of the total ownership cost is "locked-in" by design decisions. Developers and planners require an approach to estimate the O&S cost impact of design changes quickly and with credibility. This includes identification of key O&S cost drivers, uncertainty, sensitivities and risk. Linking product and process models with built-in intelligence to sources of cost information will facilitate design trade-offs and help maintain a "living" cost estimate throughout the system's life cycle. This will ensure new military systems are both effective and affordable. This SBIR will enhance an existing O&S cost methodology and computer toolset that currently estimates system life-cycle costs. The existing toolset is the basis for affordability tools within several Air Force acquisition and research organizations. The Phase I program will demonstrate the feasibility of the enhanced capabilities to include seamless operation across the enterprise function and life cycle phases. The Phase II program will fully develop a prototype tool, validate its functionality, and deliver it. |
| GALORATH, INC.
100 North Sepulveda Blvd., Suite 1801 El Segundo, CA 90245 | |
| Phone:
PI: Topic#: |
(310) 414-3222
Ms. Karen McRitchie OSD 05-CM2 Awarded: 29AUG06 |
| Title: | Automated, Intelligent Life-Cycle Cost Modeling |
| Abstract: | While suitable estimating methods exist to compute life cycle cost of systems, they can be difficult due to limited information available, especially in the early phases of a program. Another shortcoming is that they are often tied to static cost factors that give the cost analyst little to no understanding of design options on life cycle cost. Budgetary limitations and other constraints dictate that life cycle costs, particularly operations and support, need to be well understood before costs are locked in due to design decisions. Galorath will develop a framework for intelligent, automated life cycle costing that empowers the analyst to evaluate life cycle cost in a meaningful effective manner. Key focus areas will include the ability to estimate at any phase from concept to retirement, the ability to react to design decisions al all levels, from system configuration to detail parts, and the ability to transition from estimated values to known costs as a program progresses. The model would ideally be developed as a plug-in to Galorath's SEER-H hardware life cycle costing model. This model is currently used to cost systems of various sorts and the SEER-H customer base would be receptive first adopters of this enhancement. |
| IMPACT TECHNOLOGIES, LLC
200 Canal View Boulevard Rochester, NY 14623 | |
| Phone:
PI: Topic#: |
(585) 424-1990
Dr. Michael J. Roemer OSD 05-CM2 Awarded: 31AUG06 |
| Title: | Automated, Intelligent Life-Cycle Cost Modeling |
| Abstract: | DoD is continually focusing on improving weapon system affordability through the use of automated, integrated computer systems dedicated to advanced logistics and support concepts, yet current cost models for acquisition, development and operations/support are typically performed independently and often do not account for newer technologies, such as condition-based maintenance (CBM+) that will help reduce future Operating and Support (O&S) costs. Impact and Boeing Phantom Works have teamed together to develop an integrated cost simulation capability to be used during program acquisition to accurately predict weapon system life-cycle costs. This will include updated cost models at the core of the architecture with surrounding databases that will be used to automatically populate required inputs. The application will be constructed with open systems architecture to facilitate data retrieval from disparate DoD databases, and will link component cost estimates with process related effects such as differing maintenance scenario. Parametric cost estimation will be employed at early phases of development when little data is available for the new system. Additionally, Impact will leverage previously developed/validated DoD engineering based O&S cost models when simulation, test and operational data become available. The combination of parametric and engineering cost modeling will enhance cost estimation as system development progresses. |
| GALORATH, INC.
100 North Sepulveda Blvd., Suite 1801 El Segundo, CA 90245 | |
| Phone:
PI: Topic#: |
(310) 414-3222
Mr. Lee Fischman OSD 05-CM3 Awarded: 14SEP06 |
| Title: | Requirements-Based Cost Models |
| Abstract: | Large capital systems, particularly military hardware, are expected to last many years longer than the refresh cycle of their component technologies. Weapons systems will be fielded containing relatively obsolescent components, perhaps even before initial deployment. The question is, to what extent should obsolescence be allowed to impact mission requirements, and how can obsolescence costs best be mitigated? In today's cost estimating models, obsolescence is not even directly accounted for, despite its impact. As the pace of technological change quickens and technologies obsolesce more rapidly, the need to plan for and mitigate its effects will grow. Galorath will develop a complete obsolescence planning system and fully integrate this into its SEER-H hardware cost prediction tool. This will enable seamless integration of obsolescence awareness and planning with a complete development, production, operations and support cost analysis tool. SEER-H is among the most widely used, commercially available hardware costing solutions. The addition of obsolescence planning would translate into instant customer success and leverage DoD goals as an already large and growing user base gains access to it. These users are largely Defense contractors who would thus be able to engage in more sophisticated obsolescence planning for Government systems. |
| INRAD
11020 Solway School Road Knoxville, TN 37931 | |
| Phone:
PI: Topic#: |
(865) 927-4134
Ms. Mary Ann Merrell OSD 05-CM3 Awarded: 12SEP06 |
| Title: | Requirements-Based Cost Models |
| Abstract: | Accurate projection of costs remains an intractable problem in the defense industry despite more than a decade of focus on affordability. The impact to DoD acquisition programs, from cost escalation and the cost of countering capability shortfalls, runs to billions of dollars annually. The objective of this proposal is to develop and demonstrate an ontology-based framework for requirements-based cost modeling. On-tologies offer a unique capability to manage the large knowledge bases and rule sets essential to understanding cost relationships in complex systems. InRAD's innovative approach uses a systems concept where domain-specific, plug-in compatible ontologies are populated with relevant knowledge for the products, processes, materials, and functions that must be considered in cost model. Product require-ments, captured using SLATE, DOORS, or similar tools, will be used to create a requirements-based life-cycle cost modeling framework structured to align with the ontology set. The resulting capability will enable engineering and production staff to draw on a far larger base of knowledge in projecting costs; re-fine estimates faster and with greater precision; better account for uncertainties and risks; and recalculate "on the fly" when requirements change or are traded off to define the optimal balance of cost and per-formance. |
| INTEGRATED PROJECT MANAGEMENT, INC.
10008 National Boulevard, Suite 222 Los Angeles, CA 90034 | |
| Phone:
PI: Topic#: |
(310) 287-0800
Mr. Joel Fleiss OSD 05-CM3 Awarded: 12SEP06 |
| Title: | Requirements-Based Cost Models (ROBUST - Requirements Ordered Budget Using Scheduling Tools) |
| Abstract: | Project cost is a primary factor in determining which projects to implement. Projects always have an explicit or implicit set of requirements between client and developer. Requirements are usually specified using an outline metaphor where key project functionality is continuously broken down into sub-requirements using sub-paragraphs to clarify the detail. Unfortunately, this metaphor makes it difficult to accurately estimate project costs because it does not: >> Uniquely identify each requirement. >> Link each requirement to one or more of the project's tasks. >> Associate percentage of cost for each project task with the relevant requirements. >> Automatically adjust for new, deleted or changed requirements in a timely manner. What is needed is a new metaphor for specifying requirements that is conducive to establishing the one-to-one or one-to-many linkage between requirements and project tasks. IPM is proposing a system that will provide the ability to assure that each requirement is: >>> Understandable same by all stakeholders. >>> Uniquely identifiable. >>> Linkable to one or more scheduled tasks. >>> Able to link |