|Acquisition Program: || Objective: ||The objectives of this task are to:
1. Characterization of Single-Event Effects in ultra-deep submicron (< 90nm) integrated circuits and
2. Development and demonstration of minimally invasive methods to mitigate SEE in ultra-deep submicron digital and analog/mixed-signal integrated circuits.
The successful outcome of this task will support the use of ultra-deep submicron integrated circuits in DoD satellite systems that will result in very significant savings in weight, power and reliability for systems that include Space Radar, Space Tracking and Surveillance Systems, TSAT and others. Each new generation of microelectronics results in performance benefits that include > 2X in integration density, > 4X in power savings and > 2X in operating speed making possible very significant improvements in system capabilities.
|| Description: ||Currently satellite systems are fabricated using a mix of commercial and radiation hardened circuits. However, the use of advanced commercial integrated circuits devices results in added complexity to mitigate SEE that can result in the mal-operation and/or destruction of devices. In many cases, the penalties in increased power, area, weight and added circuit complexity out-weigh any potential benefits and preclude the use of the advanced commercial technology.
Additionally, present methods to mitigate SEE while proven to be effective at circuits geometries > 150nm have been not proven to be adequate at integrated circuit feature sizes below 100nm.
Thus, if minimally invasive methods such as the use of alternative materials, circuit enhancements, and other innovative approaches could be developed to reduce SEE sensitivity these devices could be used with little or no penalties.
Therefore, the basic approach to accomplish this task would be to leverage commercial microelectronics at the < 90nm nodes and augment these technologies with SEE mitigation techniques that would have minimal impact on the electrical performance and manufacturability.
Additionally, the development of such methods requires the development of cost effective methods to model and simulate the SEE response of these < 90nm technologies. Without a robust modeling and simulation capability it would be both technically and economically unfeasible to develop these mitigation methods.
|| ||PHASE I:
• Identification of minimally invasive methods, including material approaches, to mitigate SEE in < 90nm microelectronics technologies including III-V and SiGe materials systems.
• Development of cost effective SEE modeling and simulation methods for < 90nm microelectronics digital and analog/mixed-signal microelectronics.
|| ||PHASE II:
• Electronic Design Automation tools (programs) that can;
o Identify design sensitivities in complex integrated circuits
o Design radiation insensitive integrated circuits
o Perform trade studies to provide optimized integrated circuits WRT radiation and electrical performance
o Analysis the radiation response of complex integrated circuits
• Technology Computer Aided Design (TCAD) tools that can:
o Provide cost effective 3-D models to support the simulation of the radiation response of nanotechnology microelectronics.
o Identify radiation sensitivities at the transistor level
• Mixed-Mode and Level Simulation systems that can effectively couple the radiation response at the transistor level to higher levels of circuit and subsystem integration (e.g. transistor response to small circuit to complex circuit to sub-system ) to support the accurate radiation response simulation up to and including the sub-system level.
• Radiation effects Product Design Kits (PDK) that combine the electrical and radiation response design and modeling parameters for a specific technology. PDKs are provided by semiconductor manufacturers to their customers to support design activities. In general a semiconductor manufacturer will develop an electrical performance and design PDK that must be then augmented with radiation performance to support customer s that require the technology to be used in a radiation environment.
• Development and demonstration of < 90nm SEE modeling and simulation methods
|| ||PHASE III DUAL USE APPLICATIONS: Use of the mitigation, modeling and simulation methods developed through this effort to support the use of advanced microelectronics for terrestrial application such a very high performance microprocessor, advanced Servers, and very large cache memories.
|| References: ||1. IEEE Transactions on Nuclear Science; December 2005, Volume 52, Number 6, Session A Single Even Effects: Mechanisms and Modeling, pages 2104-2231
2. IEEE Transactions on Nuclear Science; December 2005, Volume 52, Number 6, Session F Single Even Effects: Devices and Integrated Circuits, pages 2421-2495
3. JEDEC 57, SEE Test and Characterization Guidelines and Test Method
|Keywords: ||Single-Event Effects, Single-Event Upset, Single-Event Transients|