| ||The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), which controls the export and import of defense-related material and services. Offerors must disclose any proposed use of foreign nationals, their country of origin, and what tasks each would accomplish in the statement of work in accordance with section 3.5.b.(7) of the solicitation.|| ||STATEMENT OF INTENT: Develop/Demonstrate asynchronous logic technology for mitigating space radiation effects, an extremely high priority for this PEO
|| Objective: ||Develop/demonstrate an asynchronous design, synthesis, and simulation tool suite for GPS User Equipment (UE) applications that mitigates Single Event Effects (SEE) and Total Ionizing Dose (TID) radiation effects.
|| Description: ||Logic devices based on asynchronous (aka clockless) design methodologies have been in existence for at least 30 years. Recently, some Computer Aided Design (CAD) companies have been proposing that clockless logic design will be required for system on-a-chip integration and for scalable Intellectual Property (IP) logic blocks. Some forms of asynchronous logic design currently use a Null Convention Logic (NCL) signaling scheme to signal local process completion it has been shown to lower power and has processing speeds determined by the Integrated Circuit (IC) technology, not a system clock. However, there are substantial problems with asynchronous logic that must be overcome.
First, mainstream Application Specific Integrated Circuit (ASIC) CAD tools are generally not available for large-scale synthesis, timing analysis and layout of asynchronous designs. Novel design solutions that provide large (>50kgate) correct-by-design asynchronous logic blocks and their integration at the chip scale are to be investigated.
Second, most IC design houses avoid asynchronous design use because it can have race conditions, glitches, and timing problems that can render some complex designs unworkable. Highly automated CAD tools that create asynchronous logic that is mathematically proven to be without glitches or races for a given process and layout needs to be developed.
Third, scaling from one generation to another has proven to be difficult as the assumptions about gate delay versus interconnection delay has rendered some asynchronous designs in one generation to be non-functional without redesign in subsequent process generations. Building an asynchronous design methodology that is scalable, and retargetable to future IC generations also needs to be demonstrated.
Lastly, and most importantly, space and ground environmental effects (temperature, total ionizing radiation, single event effects, etc.) in military applications can have profound impact on the functionality of a design. Single Event Upset can flip memory states, Single Event Transients can propagate asynchronous logic pulses. Total Ionizing Dose due to electrons, protons and ions can cause increased delays in logic devices and increases in device rise times. Simulation, analysis and test tools need to be developed to address military environments and to provide robust designs that work reliably under all conditions for the application of asynchronous logic to function properly.
Three high-value GPS receiver problems that this topic will attempt to overcome are: 1) rapid direct m-code signal acquisition, 2) low power Advanced Encryption Standard (AES) cryptographic code generation, or 3) effective digital baseband jammer suppression.
|| ||PHASE I: Identify existing asynchronous design tools and their efficacy in mitigating radiation (SEE and TID) effects. Develop alternative strategies and tools to overcome current design deficiencies. Determine the technical merit and feasibility of applying these asynchronous design methods, addressing two of the problems above. Currently the GPS Modernized User Equipment program would benefit if a commercial 90 nm CMOS process were investigated, while GPS Modernized Space Receiver program would benefit if a Rad-Hard 150 nm CMOS process were investigated under Phase I.
|| || ||PHASE II: Design, simulate, prototype, package and test the GPS receiver functional blocks targeting one of the DoD Trusted Foundries. Provide sufficient test die and documentation to perform all validation testing, and supply an independent gov't test laboratory. Include VHDL design models, test benches, and documentation such that these IP blocks may be reused in higher level ASIC development.
|| ||DUAL USE COMMERCIALIZATION: Military application: Across board military applications in asynchronous logic design.(R&D) conducted under this SBIR will create products that include asynchronous design tools & space-hardening asynchronous design tools. Commercial application: R&D conducted under this SBIR will include commercial applications, such as, asynchronous design tools, space-hardening asynchronous design tools, and GPS receiver ASIC intellectual property.
|| References: ||1. Stephen H. Unger, "Asynchronous Sequential Switching Circuits," New York, Wiley-Interscience, 1969
2. Karl Fant, "Logically Determined Design: Clockless System Design with NULL Convention Logic," New York, Wiley-Interscience, 2005.
|Keywords: ||GPS, MUE, asynchronous logic, delay independent, clockless logic, scalable CMOS IP|