SITIS Archives - Topic Details
Program:  SBIR
Topic Num:  OSD10-A07 (OSD)
Title:  Incorporation of trust into integrated circuit (IC) and field programmable gate array (FPGA) design
Research & Technical Areas:  Information Systems, Materials/Processes

Acquisition Program:  
 The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), which controls the export and import of defense-related material and services. Offerors must disclose any proposed use of foreign nationals, their country of origin, and what tasks each would accomplish in the statement of work in accordance with section 3.5.b.(7) of the solicitation.
  Objective:  Develop innovative trusted intellectual property (IP) (circuit designs, embeddable micro-code, and the like) that will prevent other portions of an integrated circuit (IC) or field programmable gate array (FPGA) design from operating in modes, malicious or accidental, other than those intended by the designer.
  Description:  In the modern process of integrated circuit (IC) development, the actual design and fabrication of an IC typically is distributed between a number of different companies and/ or individuals. Often, a design house for a new IC will design some of their own intellectual property (IP) components while purchasing other IP components from other vendors. Typically, the source code for these purchased components is not available to the designer, who, instead, relies on interface control documents (ICDs) and programming interface descriptions. This requires a degree of trust between the designer and the IP vendor: the designer trusts that the vendor has listed all the functionality of the IP he is providing, and that no other functions from this IP core are possible. Additionally, in the manufacturing of devices by independent IC foundries, the foundry will often take the designer’s original design and include into it foundry-specific circuitry for testing, in order to assure yields at the wafer level. This would be another part of the design process over which the original designer has no control. Ultimately, the original designer wants to be able to assure that the final device performs only those functions for which it was designed and no others. The goal of this task is to develop IP cores that can be incorporated into a design such that the functioning of non-trusted IP can be monitored and controlled. Participation in this SBIR is limited to US Citizens.

  PHASE I: The offeror will investigate methods for unambiguously specifying the intended operation of a system. Additionally, the offeror will perform a preliminary design of IP cores or systems of IP specifically for the purpose of implementing the trusted operation as described in the first phase of this task, assuring trust in overall IC and FPGA designs. These cores will monitor the performance of other IP on the device, signaling and/or preventing anomalous, unintended operations. The performance of whatever approach is taken needs to be verified via simulation, at least to the transaction level or to whatever level is most appropriate for the proposed approach. The offeror will provide a final report to the government.
  PHASE II: In the second phase, the contractor will more fully develop the approaches determined to be most promising in Phase I. The contractor will propose a system based on a mix of IP. The offerer will demonstrate that, even if a piece of IP on the system performs in a malicious way (i.e. it is malware), the integrity of the overall system is not compromised. Ideally, by the end of Phase II, the offerer should be able to demonstrate this in an FPGA environment. The offeror will provide a two day on site seminar covering the IP components and the system. The offeror will provide a final report to the government.

  PHASE III: Dual Applications: Department of Defense Directive (DOD) 5000.2R provides instructions on identifying critical technologies and on defining methods to protect them. Commercialization opportunities exist throughout the Defense Department and within the government agencies such as the Department of Homeland Security and Intelligence Community for technologies to protect critical technologies. Commercial applications include manufacturing companies who want to protect their IP during the design/fabrication of hardware and software.

  References:   [1] Adee, Sally, IEEE Spectrum, “The Hunt for the Kill Switch,” http://www.spectrum.ieee.org/semiconductors/design/the-hunt-for-the-kill-switch/0 [2] Pope, S., “Trusted Integrated Circuit Strategy,” IEEE Transactions on Components and Packaging Technologies, vol. 31, iss. 1, March 2008, pgs. 230-234. [3] Trimberger, S, “Trusted Design in FPGAs,” Design Automation Conference, 2007, DAC ’07, 44th ACM/IEEE, o4-08 June 2007, pgs. 5-8. [4] Verbauwhede, I. , Schaumont, P, “Design Methods for Security and Trust,” Design, Automation & Test in Europe Conference and Exhibition, 2007, DATE ’07, 16-20 April 2007, pgs. 1-6.

Keywords:  IC, FPGA, Trusted Intellectual Property (IP), Trusted Design, Trusted Operation

Questions and Answers:
Q: Which "DoD Component" on the DoD SBIR/STTR Web site should this topic be submitted under, i.e. OSD/Air Force, OSD/Army, OSD/DARPA, or OSD/Navy?
A: For questions about submitting a SBIR proposal, please contact the SBIR Helpdesk at 866-SBIRHLP (724-7457) or http://www.dodsbir.com/helpdesk/default.htm.
Q: Is there a preference between real-time solution and a power-up/reset time solution?
A: The intent of the solicitation is for a real-time solution.

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