SITIS Archives - Topic Details
Program:  SBIR
Topic Num:  DMEA102-002 (DMEA)
Title:  Broadband Quadrature Mixers and I/Q Mismatch Reduction
Research & Technical Areas:  Sensors, Electronics

Acquisition Program:  
 The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), which controls the export and import of defense-related material and services. Offerors must disclose any proposed use of foreign nationals, their country of origin, and what tasks each would accomplish in the statement of work in accordance with section 3.5.b.(7) of the solicitation.
  Objective:  Design a broadband in-phase/quadrature-phase (I/Q) modulator and demodulator suitable for fabrication using an industry-utilized Silicon-on-Sapphire (SoS) process. Because I/Q mismatch is a prevalent source of error in quadrature mixing, a novel approach to reduce or mitigate gain and phase error will be investigated and developed for use in radio frequency (RF) System-on-Chip (SoC) applications, particularly low power, single chip transceivers.
  Description:  Cliché characteristics in a desirable transceiver design are low power consumption, high bandwidth, small form factor, and low cost with the versatility of implementing every modulation technique across a broad frequency spectrum. As technology evolves, we get closer and closer to approaching that goal, and a key area for research and design is I/Q modulation and demodulation. Single chip transceivers are implemented in low-IF and zero-IF architectures aimed at the goals listed above. For example, smaller form factors are possible because use of external filters are minimized or negated, power consumption is lessened with the use of a single LO, and cost is reduced with the high level of integration to realize the entire transceiver on a single chip. A design issue encountered with quadrature mixers is I/Q imbalance. Gain and phase errors in the I and Q branches can degrade the overall performance of a receiver, for example, reduction in image rejection in a heterodyne architecture or intercarrier interference in a zero-IF OFDM architecture. Multiple solutions have been devised in the past decade to resolve the issue of I/Q imbalance, but these solutions entailed the use of DSP. The objective of this research is to reduce or mitigate the I/Q imbalance without the use of DSP algorithms while minimizing power consumption. Research will be done to investigate and develop a novel architecture modification or calibration technique with quadrature mixers. The development of IP blocks for RF SoCs continues to be a goal for commercial and military designers. The availability of broadband quadrature mixers for I/Q modulation and demodulation with minimal I/Q mismatch can provide a key block with the versatility to be inserted in multiple transceiver architectures implemented with various modulation techniques. In particular, the availability of quadrature mixers fabricated using SoS is limited, and development of such a device would lend itself to the growth of an IP library implemented in SoS.

  PHASE I: Research existing I/Q modulator and demodulator implementations and techniques to reduce or mitigate I/Q mismatch. Conceive a novel approach and design the top level system of the I/Q modulator and demodulator. The aim of the innovation is to reduce or mitigate I/Q mismatch while meeting targeted performance specifications and area/power consumption constraints. Determine all architectural decisions keeping in mind its implementation using an industry-utilized SoS process. The report will present the tradeoffs between the new approach and existing technology. The schematic design will be completed, and simulations over process, temperature, and supply variations should meet the provided specifications and accompanying requirements. Specifications include: I/Q Demodulator - Input Frequency Range: 0.1GHz to 3.0GHz - 50 ohm AC-Coupled Single-Ended RF and LO Ports - IIP3: > 20dBm - IIP2: > 50dBm - Input P1dB: > 12dBm - I/Q Gain Mismatch: ±0.02dB - I/Q Phase Mismatch: ±0.2° - Output DC Offset: < 10mV - Noise Figure: < 13dB - LO to RF Leakage: < -60dBm - RF to LO Isolation: < -60dBc - RF Input Return Loss: > 15dB - LO Input Return Loss: > 15dB - Supply Voltage: 3.0V ± 10% - Current Consumption: 100mA - Current Consumption (shutdown): < 1microA - Operating Temperature: -55°C to 125°C - Area: 2.5mm2 I/Q Modulator - Input Frequency Range: 0.1GHz to 3.0GHz - 50 ohm AC-Coupled Single-Ended RF and LO Ports - OIP3: > 20dBm - OIP2: > 50dBm - Output P1dB: > 10dBm - I/Q Gain Mismatch: ±0.02dB - I/Q Phase Mismatch: ±0.2° - LO Feedthrough: < -50dBm - RF Output Return Loss: > 15dB - LO Input Return Loss: > 15dB - Supply Voltage: 3.0V ± 10% - Current Consumption: 100mA - Current Consumption (shutdown): < 1 microA - Operating Temperature: -55°C to 125°C - Area: 2.5mm2 If any of the goals listed above cannot be met, the contractor will present relevant research and establish parameters that are attainable. The system will include any peripheral blocks on chip including, but not limited to, baseband filters, buffers/drivers, phase shifters/generators, bias circuitry, transformers/baluns, and ESD protection. The contractor will report on all findings/procedures and provide all CAD generated files, for example, schematics and simulation test benches.
  PHASE II: Complete the layout of the design developed in Phase I. Re-verify the performance over process, temperature, and supply variations including extracted parasitics with the final schematic and layout iteration. The contractor will fabricate the design using a SoS fabrication line approved by the Government. The contractor will develop a test board and test plan to characterize the prototypes. The contractor will test the prototypes and deliver the parts, characterization results, all CAD generated files, and the test plan to the Government for further testing and verification.

  PHASE III: There may be opportunities for further development of these devices for use in a specific military or commercial application. During a Phase III program, the contractor will refine the performance of the design and produce pre-production quantities for evaluation by the Government. POTENTIAL DUAL USE APPLICATIONS: The I/Q modulator and demodulator will be applicable to both commercial and military semiconductor device research and design. Military applications include integration on a board level system or an RF SoC for use in future wireless designs or existing fielded communication systems and sensors. Commercial functions include any wireless application such as cell phones or wireless networks.

  References:  1. B. Razavi, “Design considerations for direct-conversion receivers,” IEEE Trans. Circuits Syst. II, vol. 44, pp. 428 – 435, Jun. 1997. 2. M. Valkama, M. Renfors, and V. Koivunen, “Advanced methods for I/Q imbalance compensation in communication receivers,” IEEE Trans. on Signal Proc., vol. 49, pp. 2335 – 2344, Oct. 2001. 3. L. Anttila, M. Valkama, and M. Renfors, “Blind compensation of frequency-selective I/Q imbalances in quadrature radio receivers: circularity-based approach,” in Proc. IEEE Int. Conf. on Acoustics, Speech and Signal Processing, vol. 3, pp. III-245 – III-248, Apr. 2007. 4. G. Gil, Y. Kim, and Y. Lee, “Non-data-aided approach to I/Q mismatch compensation in low-if receivers,” in IEEE Trans. on Signal Processing, vol. 55, pp. 3360 – 3365, Jul. 2007.

Keywords:  RF Integrated Circuit, RF System-on-Chip, RF Component, Quadrature Mixer, I/Q Mismatch, Microelectronics, Silicon-on-Sapphire, Transmitter, Receiver, Transceiver

Questions and Answers:
Q: Are software based compensation techniques discouraged?
A: A desirable product of this research is a self-contained/stand-alone solution with the flexibility to be inserted into various systems where the I/Q mod and demod function without the additional need for a microcontroller or DSP.

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