|Acquisition Program: || Objective: ||Develop design tools which enable electronic circuit designs leveraging highly regular geometries such as grating-derived line segments. Such Design methodologies have the dual benefit of simplifying the design and fabrication processes as well as lowering the cost of the low volume circuit design and fabrication needs of the DoD.
|| Description: ||An ongoing challenge for the DoD in the electronics domain is performance required in a cost effective manner for the low unit volumes typical of Defense systems (relative to the commercial electronics world). Highest performance in terms of both speed and power efficiency is typically achieved using custom application specific circuits (ASICs). These chips are currently quite costly to design and fabricate using today’s methods optimized for high volume commercial applications.
The purpose of this SBIR is to help develop novel circuit design methodologies leveraging highly regular geometries such as grating-derived line segments. More specifically, this SBIR calls for the development of software and CAD tools that can enable efficient design using such highly regular circuit geometries. Efficient conversion of legacy designs into such highly regular (1D) geometries is also a goal of this SBIR.
The design tools developed with this SBIR will enable the simplification of the complex IC design process as well as help lower the design and fabrication costs for the low volume, high performance ASICs that the DoD desires. This simplification in design should not sacrifice performance metrics such as speed, power and efficiencies of the ICs. The resulting cost savings will vary depending on the design complexity, technology nodes, process technology, fabrication equipment, and production volume. However, the cost savings will be significant for DoD low volume production of complex ASICs.
|| ||PHASE I: Demonstrate the feasibility of the specific highly regular design approach to produce circuits of good performance (speed and density for example). Examples of some common standard digital cells might be an example output of this phase.
|| ||PHASE II: Based on the preliminary work in phase I, a more complete set of standard cell library elements will be developed based on highly regular (1D) geometries. These circuit cells will have competitive performance with respect to speed and density to modern state of the art CMOS (Complementary Metal Oxide Semiconductor). For demonstration and validation of the simplified design and the associated circuit performance, test patterns, functional cells or blocks incorporating the novel high regular designs will be fabricated and tested via either MOSIS or TAPO services.
|| ||PHASE III: Software tools for highly regular (1D) designs for the sub-20nm CMOS (Complementary Metal Oxide Semiconductor) technology nodes should be broad enough to interest BOTH DoD and commercial low-volume applications. Commercial applications include rapid prototyping or Application Specific Integrated Circuits (ASICs.)
These new design tools should simplify the design costs for complex IC designs thus lowering the cost and improving manufacturability. Particular emphasis will be placed on lowering the high design and fabrication costs of the ASICs that the DoD desires for high performance, power efficient applications. These new design tools should simplify the design costs for complex IC designs thus lowering the cost and improving manufacturability. Particular emphasis will be placed on lowering the high design and fabrication costs of the ASICs that the DoD desires for high performance, power efficient applications.
|| References: ||
1. Lin Zhao and M. Qi, “Generating Manhattan Patterns via Cutting and Stitching of Gratings” 52nd EIPBN Meeting, Portland, Oregon, May, 2008
2. Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner "Lithography-Layout-Circuit Design Co-optimization in the Extremely Regular Layout IC's”, Lithography Workshop 2009
3. Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej J. Strojwas, et al., "Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity", Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 6 (03), 2007.
4. Michael C. Smayling, Hua-yu Liu, Lynn Cai “Low k1 Logic Design using Gridded Design Rules”, SPIE Advanced Lithography Conference, Feb 2008|
|Keywords: ||Circuit design, electronics, low volume fabrication, computer-aided design|